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| TENTATIVE SPDT SWITCH GaAs MMIC GENERAL DESCRIPTION NJG1600KB2 is a GaAs SPDT switch IC that features small-sized package and low insertion loss , and ideally suited for T/R switch of digital cordless telephone or other digital wireless systems. This switch is operated in the wide frequency range from 100MHz to 2.5GHz at low operating voltage from +2.5V. The ultra small & ultra thin FLP6-B2 package is adopted. FEATURES Low control voltage Low insertion loss NJG1600KB2 Mar.22,2002 Ver.2 Under Development PACKAGE OUTLINE NJG1600KB2 High isolation +2.7V typ. 0.3dB typ. @f=1.0GHz 0.35dB typ. @f=2.0GHz 0.4dB typ. @f=2.5GHz 25dB typ. @f=1.0GHz 18dB typ. @f=2.0GHz 17dB typ. @f=2.5GHz 27dBm typ. @f=2.5GHz 15uA typ. FLP6-B2 (Package size: 2.1x2.0x0.75mm) Pin at 1dB compression point Low control current Ultra small & ultra thin package PIN CONFIGURATION Orientation Mark KB2 Type Top view 1 2 3 6 5 4 Pin connection 1.P1 2.GND 3.P2 4.VCTL2 5.PC 6.VCTL1 TRUTH TABLE "H"=VCTL (H), "L"=VCTL (L) VCTL1 VCTL2 PC - P1 PC - P2 H L OFF ON L H ON OFF -1- NJG1600KB2 ABSOLUTE MAXIMUM RATINGS PARAMETER RF Input Power Supply Voltage Control Voltage Operating Temp. Storage Temp. SYMBOL PIN VDD VCTL Topr Tstg TENTATIVE CONDITIONS VDD=2.7V, VCTL=0V/2.7V VDD terminal VCTL terminal CONDITIONS 27 7.5 7.5 -40~+85 -55~+150 UNITS dBm V V C C ELECTRICAL CHARACTERISTICS (General conditions: VCTL (L)=0V, VCTL (H)=2.7V, ZS=Zl=50, Ta=25C) PARAMETERS Operating Current Control Voltage (LOW) Control Voltage (HIGH) Control Current SYMBOL CONDITIONS MIN TYP 120 2.7 15 0.3 0.35 0.4 25 18 17 27 1.4 100 MAX 0.8 VDD 30 0.4 0.45 0.5 1.6 - UNITS uA V V uA dB dB IDD VCTL (L) VCTL (H) ICTL LOSS1 LOSS2 LOSS3 ISL1 ISL2 ISL2 P-1dB VSWR TSW f=2.5GHz, PIN=22dBm 0 2.0 f=2.5GHz, PIN=22dBm f=1.0GHz, PIN=22dBm f=2.0GHz, PIN=22dBm f=2.5GHz, PIN=22dBm f=1.0GHz, PIN=22dBm f=2.0GHz, PIN=22dBm f=2.5GHz, PIN=22dBm f=2.5GHz f=0.1~2.5GHz, ON state f=0.1~2.5GHz 22 15 14 24 - Insertion Loss 1 Insertion Loss 2 Insertion Loss 3 Isolation 1 Isolation 2 Isolation 3 Pin at 1dB Compression Point VSWR Switching time dB dB dBm ns -2- TENTATIVE TERMINAL INFORMATION NJG1600KB2 No. 1 SYMBOL P1 2 GND 3 P2 4 VCTL2 5 PC 6 VCTL1 DESCRIPTION RF port. This port is connected with PC port by controlling 4th pin (VCTL(H)) to 2.5~6.5V and 6th pin(VCTL(L)) to -0.2~+0.2V. An external capacitor is required to block the DC bias voltage of internal circuit. (50~100MHz:0.01uF, 0.1~0.5GHz: 1000pF, 0.5~2.5GHz: 56pF) Ground terminal. Please connect this terminal with ground plane as close as possible for excellent RF performance. RF port. This port is connected with PC port by controlling 6th pin (VCTL (H)) to 2.5~6.5V and 4th pin(VCTL(L)) to -0.2~+0.2V. An external capacitor is required to block the DC bias voltage of internal circuit. (50~100MHz:0.01uF, 0.1~0.5GHz: 1000pF, 0.5~2.5GHz: 56pF) Control port 2. The voltage of this port controls PC to P1 state. The `ON' and `OFF' state is toggled by controlling voltage of this terminal such as high-state (2.5~6.5V) or low-state (-0.2~+0.2V). The voltage of 6th pin have to be set to opposite state. The bypass capacitor has to be chosen to reduce switching time delay from 10pF~1000pF range. Common RF port. In order to block the DC bias voltage of internal circuit, an external capacitor is required. (50~100MHz:0.01uF, 0.1~0.5GHz: 1000pF, 0.5~2.5GHz: 56pF) Control port 1. The voltage of this port controls PC to P2 state. The `ON' and `OFF' state is toggled by controlling voltage of this terminal such as high-state (2.5~6.5V) or low-state (-0.2~+0.2V). The voltage of 4th pin have to be set to opposite state. The bypass capacitor has to be chosen to reduce switching time delay from 10pF~1000pF range. -3- NJG1600KB2 APPLICATION CIRCUIT Zo=50 P1 C2 2 Zo=50 P2 C3 3 1 TENTATIVE VCTL1 (0V/2.7V) 6 5 R1 4 NJG1600KB2 C5 VCTL2 (2.7V/0V) C4 C1 Zo=50 PC Parts List Parts ID C1~C3 C4, C5 R1 Constant 56pF 10pF 560K Notes GRM36 MURATA GRM36 MURATA 1608 Size RECOMMENDED PCB DESIGN (TOP VIEW) C3 P2 C5 R1 VCTL2 C3 PC C2 C4 VCTL1 P1 PCB SIZE=19.4x14.0mm PCB: FR-4, t=0.2mm CAPACITOR: size 1005 STRIPLINE WIDTH=0.4mm PRECAUTIONS [1] The DC blocking capacitors have to be placed at RF terminal of P1, P2 and PC. [2] To reduce stlipline influence on RF characteristics, please locate bypass capacitors (C4, C5) close to each terminals. [3] To avoid degradation of isolation or high power characteristics, please layout ground pattern right under this IC. . -4- NJG1600KB2 PACKAGE OUTLINE (FLP6-B2) 2.00.1 6 5 4 0.2 0.750.05 +0.1 0.15 -0.05 1.70.1 1 0.65 2 0.65 3 0.2 2.10.1 0.1 Lead material : Copper Lead surface finish : Solder plating Molding material : Epoxy resin UNIT : mm Weight : 6.5mg +0.1 0.2 -0.05 0.1 Cautions on using this product This product contains Gallium-Arsenide (GaAs) which is a harmful material. * Do NOT eat or put into mouth. * Do NOT dispose in fire or break up this product. * Do NOT chemically make gas or powder with this product. * To waste this product, please obey the relating law of your country. [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. This product may be damaged with electric static discharge (ESD) or spike voltage. Please handle with care to avoid these damages. -5- |
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